Field of the Invention
The present invention relates in general to address translations performed by a processor, and more particularly to a load extended page table (EPT) instruction that may be executed when virtualization is enabled to directly convert a guest physical address into a true physical address.
Description of the Related Art
Modern processors support virtual memory capability. A virtual memory system maps, or translates, virtual (a.k.a., “linear”) addresses used by a program to physical addresses used by hardware to address system memory. Virtual memory provides the advantages of hiding the fragmentation of physical memory from the program and facilitating program relocation. Virtual memory thus allows the program to see a larger memory address space than the actual physical memory available to it. These advantages are particularly beneficial in modern systems that support time-sharing of the processor by multiple programs or processes.
An operating system (OS) implements the virtual memory system by creating and maintaining in system memory translation tables, often referred to as page tables, in a paged virtual memory system. The page tables map virtual addresses to physical addresses of system memory coupled to the processor. The translation tables may be in the form of a hierarchy of tables, some of which map virtual addresses to intermediate table addresses. When a program accesses memory using a virtual address, the translation tables are accessed in sequential order to accomplish the translation of the virtual address to its physical address, commonly referred to as a page table walk, or “tablewalk.”
Many processors also support virtual machine extensions (VMX) that enable virtualization of the processor hardware for multiple software environments. As described in Chapter 28 of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3C: System Programming Guide, January 2015 (referred to herein as the “Intel® system programming guide”), which is hereby incorporated by reference in its entirety for all intents and purposes, the architecture includes two features that support address translation for VMX operation, including virtual-processor identifiers (VPIDs) and the extended page-table (EPT) mechanism. VPIDs provide a mechanism for translations of virtual addresses, whereas the EPT mechanism defines a layer of address translation that augments the translation of the virtual addresses. A hypervisor or the like virtualizes system resources to enable multiple independent operating systems to share the same hardware resources. Each OS implementing a virtual memory system is unaware, however, that its page tables are also virtualized. Each “physical address” of an OS is instead treated as a “guest” physical address that must be further translated through a set of EPT paging structures to produce a “true” physical address that may be used to access the system memory.
When virtualization is active, the EPT mechanism is nested within the normal tablewalk process to convert each guest physical address from the page tables into a corresponding true physical address to access the actual corresponding page table stored in the system memory. The EPT mechanism includes an EPT tablewalk engine that supplements the tablewalk process by accessing the EPT paging structures to convert guest physical addresses into true physical addresses. In this manner, multiple EPT conversions are performed during each tablewalk in a virtualized system architecture.
Conventional processors that support virtual machine extensions to enable virtualization of the processor hardware for multiple software environments often include the EPT translation mechanism for conversion of virtual addresses into physical addresses to access system memory. Conventional processors do not, however, have a mechanism to directly convert a guest physical address into a true physical address apart from the standard address translation process.